The present invention relates to semiconductor processing and, more particularly, to a method for the manufacture of field-effect transistors. A major objective of the present invention is provide for improved submicron field-effect transistors.
Modern technological progress has resulted from the increasing miniaturization of integrated circuit elements made possible by advances in semiconductor processing technology. One of the most important circuit elements made possible by semiconductor processing is the IGFET (Insulated-Gate field-effect transistor). IGFETS are more popularly known as "MOS" transistors or "MOSFETs" (Metal-Oxide-Silicon Field-Effect Transistors). MOS is an acronym for "Metal-Oxide-Silicon". Early MOS devices used metal gates. While polysilicon is currently the gate material of choice today, "MOS" is a well-entrenched misnomer.
AMOS transistor typically functions as a voltage-controlled current switch. The basic components of the MOS transistor are: a source that serves as a current input; a drain that serves as a current output; a channel that selectively couples the source and drain; and a gate that controls the conductivity of the channel. When a forward voltage bias is applied between the source and the drain, the current from the source through the channel to the drain is controlled by the gate voltage.
Most of the early MOS transistors were n-channel devices fabricated using p-type substrates; subsequently, p-channel devices fabricated using N-type substrates predominated. ("n" stands for "negative" and "p" for positive. Of increasing importance is CMOS technology ("C" for "complementary"), that utilizes both n-channel devices and p-channel devices to produce devices with high-speed and lower power consumption.
PMOS processing typically begins with a crystalline silicon substrate that is lightly doped n-type. The n-type dopant is typically phosphorous or arsenic. A dopant is n-type if the majority of charge carriers in the doped silicon are negatively charged electrons. A dopant is p-type if the majority of charge carriers in the doped silicon are positively charged electron holes. A gate oxide is grown over the substrate. Gate material (metal or polysilicon) is deposited over the gate oxide. The polysilicon and the gate oxide are photolithographically patterned to form the gate. P-type dopant is introduced outside the gate to define the source and the drain; the gate masks the channel region directly below, so the channel remains n-type. NMOS technology is similar except that the conductivity types are reversed.
CMOS technology typically begins with an n-type substrate. P-type wells are defined for the p-channel devices. Generally, additional doping is used to define n-wells for the n-channel devices. A boron implant is applied to both the n-wells and the p-wells to establish a suitable voltage threshold for the channels. The gate oxides, the gates, the sources and the drains for both types of transistors can be formed as in NMOS and PMOS technologies.
One of the obstacles to progress in MOS technology is the tendency for the breakdown voltage to fall with decreasing transistor size. The drain-to-source breakdown voltage BV.sub.dss is the reverse-bias voltage at which current can be made to flow from drain to source when the gate is off. This current condition signifies an unintended performance of the transistor. Accordingly, a relatively high breakdown voltage is desired for device protection. It is desirable to maintain a breakdown voltage at least twice the normal operating voltage. Thus, for a typical five-volt system, the transistors should have breakdown voltages of 10 volts or more.
As a first approximation, the breakdown voltage can be considered a function of the length and depletion width. A long channel provides a high breakdown voltage. The relative importance of the length depends on the magnitudes, with the lesser magnitude dimension having a more substantial impact on the breakdown voltage.
At large geometries, the channel length is substantially equal to the feature size. Thus, for a 2-3 micron (.mu.m) technology, the channel length is 2-3 microns. The depletion width is determined by the dopant concentration in and under the channel. This concentration is usually determined by the system requirement that the turn-on voltage for the transistor be nominally 0.7 volts. The depletion width under these circumstances is usually about 1 .mu.m or less. It turns out that breakdown voltages of 15 volts are readily achieved with these channel dimensions.
Higher breakdown voltages can be achieved using a "punch-through" implant which increases the concentration of channel type dopant below the channel (where breakdown typically occurs). The phrase "punch through" is essential equivalent to "breakdown", as in "breakdown voltage". The punch-through implant is performed before the gate is formed. Channel-type dopant is implanted to a depth below the channel so that the channel dopant concentration is not substantially affected. The increased background concentration effectively reduces the depletion width, increasing the breakdown voltage. For 2-3 .mu.m devices, breakdown voltages of 25 volts or more can be achieved. This is useful, for example, for input/output transistors.
With advances in semiconductor processing technology, feature sizes, and thus channel length have dropped well below 1 .mu.m. To maintain 0.7 volt turn on, channel concentrations have increased, decreasing depletion width. However, reductions in depletion width have not kept pace with reductions in channel length, so channel length is a significant consideration for breakdown voltages at 0.8 .mu.m technology and below.
Accordingly, any loss of channel length for a given feature size can be costly in terms of reduce breakdown voltage. A reduction in channel length can occur due to lateral diffusion of the source and drain dopant. As feature size is decreased, it becomes increasingly important to limit this lateral diffusion of the source/drain dopant.
A halo implant, also called a "pocket implant", has been used to limit lateral diffusion of the source and drain dopant. The halo implant is of the conductivity type opposite that of the source and drain. Like the source/drain implant, it is performed after the gate is defined and before the source/drain diffusion. Due to the masking effect, the halo implant peak concentration is near the source/drain regions. Away from the source/drain edge, the depth of the peak halo concentration falls quickly. The halo implant energy is set so that the peak concentration depth away from the peak is greater than the depth of the source/drain implant so that the vertical source drain diffusion is not impeded. However, the relatively vertical halo profile below the gate edge acts as a barrier to lateral diffusion of the source/drain dopant. Thus, the channel length can be maintained at the length corresponding to the gate dimension.
The effectiveness of the halo implant in limiting lateral diffusion of the source/drain dopant depends on the halo concentration. However, too high a halo concentration adversely affects channel characteristics. For example, threshold voltage roll-off is distorted and a hot-carrier effect is aggravated. To limit these adverse affects, halo concentration must be limited. Thus, lateral diffusion remains a concern and breakdown voltage unsatisfactorily low. Further control of lateral diffusion of the source/drain dopant is required to enhance the reliability of submicron MOS transistors and to provide for further reductions in device dimensions.